Integrated circuit (IC) process limitations associated with decreasing minimum feature size tend to favor dummy polycrystalline silicon (poly) segments formed on edges of a silicon oxide definition (OD) region such as an active region of a standard cell, i.e., poly-on-OD-edge (PODE). PODE helps to ensure that active poly fingers are properly formed and performance degradation due to faceting of transistors near the edges of the OD region is prevented. For example, abutted standard cells may include active poly segments in two PODEs.
If two standard cells are abutted to one another, such as a cell A and a cell B are abutted, the PODE and the OD region of cell A and the PODE and the OD region of cell B are separated in order to prevent inter-cell leakage current flowing between the two abutted cells. Intra-cell current leakage occurs if the abutted standard cells have separated independent PODEs, and OD regions, and inter-cell leakage current is essentially negligible. However, separated standard cells use extra spacing between OD regions of the two abutted standard cells, which correspondingly incurs additional IC area penalty.